In recent years, there has been rising demand for an information processing apparatus (server) of a multiprocessor configuration having a data processing unit mounting a plurality of processors, that is, a system board (SB), and transferring data between a plurality of SBs or between an SB and an input/output control unit (IOU) to which an I/O device is connected, where the system (server) is provided with at least a first route (bus) for data communication, a second route (bus) for data communication, and a first data transfer circuit (crossbar unit) and second data transfer circuit (crossbar unit) able to suitably switch or close down these routes for data communications.
According to such a configuration of an information processing apparatus, when a fault occurs in one of the first and second route, the other communication route is used to back up the data transfer of the faulty route. Due to this, the reliability is improved. Further, it is also possible to increase the processing capability of the information processing apparatus (achieve higher throughput) by simultaneously using both the first and second routes. The present invention relates to the reduction of power or saving of power in such an information processing apparatus.
Note that, as examples of the known art relating to power saving designs, there are the “communication control device” of Patent Document 1, the “system buffer control device” of Patent Document 2, etc.
Patent Document 1: Japanese Laid-Open Patent Publication No. 11-27292
Patent Document 2: Japanese Laid-Open Patent Publication No. 5-334107
In the information processing apparatus of the related art, at the time of ordinary operation, the first and second routes (buses) are both simultaneously placed in the operating state. For this reason, the first and second data transfer circuits (crossbar units) are both constantly supplied with power and clocks unless a fault occurs in one of them.
That is, regardless of the magnitude of the data processing rate required in an information processing apparatus, the first and second data transfer circuits are constantly in a power consuming state.